A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO

Accelerating deep learning networks in edge computing based on power-efficient and highly parallel FPGA platforms is an important goal. Combined with deep learning theory, an accelerator design method based on the Winograd algorithm for the deep learning object detection model YOLO under the PYNQ ar...

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Main Authors:	Chun Bao, Tao Xie, Wenbin Feng, Le Chang, Chongchong Yu
Format:	Article
Language:	English
Published:	IEEE 2020-01-01
Series:	IEEE Access
Subjects:	FPGA deep learning Winograd YOLO buffer pipeline
Online Access:	https://ieeexplore.ieee.org/document/9094705/

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spelling	doaj-3f0f1c76752b4dab93b60706207cb78e2021-03-30T03:02:10ZengIEEEIEEE Access2169-35362020-01-018943079431710.1109/ACCESS.2020.29953309094705A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLOChun Bao0https://orcid.org/0000-0002-5177-6808Tao Xie1Wenbin Feng2Le Chang3Chongchong Yu4School of Computer and Information Engineering, Beijing Technology and Business University, Beijing, ChinaSchool of Computer and Information Engineering, Beijing Technology and Business University, Beijing, ChinaState Key Laboratory of Coal Mine Safety Technology, Fushun, ChinaSchool of Computer and Information Engineering, Beijing Technology and Business University, Beijing, ChinaSchool of Computer and Information Engineering, Beijing Technology and Business University, Beijing, ChinaAccelerating deep learning networks in edge computing based on power-efficient and highly parallel FPGA platforms is an important goal. Combined with deep learning theory, an accelerator design method based on the Winograd algorithm for the deep learning object detection model YOLO under the PYNQ architecture is proposed. A Zynq FPGA is used to build the hardware acceleration platform of a YOLO network. The Winograd algorithm is used to improve traditional convolution. In the FPGA, the numerous multiplication operations in the YOLO network are converted into addition operations, reducing the computational complexity of the model. The data of the original model are processed at a low fixed point, reducing the resource consumption of the FPGA. To optimize memory, a buffer pipeline method is proposed, which further improves the efficiency of the designed accelerator. Experiments show that compared with the acceleration of the YOLO model based on GPUs and other FPGA platforms, the proposed method not only optimizes FPGA resource usage but also reduces power consumption to 2.7 W. Additionally, the detection accuracy loss is less than 3%.https://ieeexplore.ieee.org/document/9094705/FPGAdeep learningWinogradYOLObuffer pipeline
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Chun Bao Tao Xie Wenbin Feng Le Chang Chongchong Yu
spellingShingle	Chun Bao Tao Xie Wenbin Feng Le Chang Chongchong Yu A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO IEEE Access FPGA deep learning Winograd YOLO buffer pipeline
author_facet	Chun Bao Tao Xie Wenbin Feng Le Chang Chongchong Yu
author_sort	Chun Bao
title	A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO
title_short	A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO
title_full	A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO
title_fullStr	A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO
title_full_unstemmed	A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO
title_sort	power-efficient optimizing framework fpga accelerator based on winograd for yolo
publisher	IEEE
series	IEEE Access
issn	2169-3536
publishDate	2020-01-01
description	Accelerating deep learning networks in edge computing based on power-efficient and highly parallel FPGA platforms is an important goal. Combined with deep learning theory, an accelerator design method based on the Winograd algorithm for the deep learning object detection model YOLO under the PYNQ architecture is proposed. A Zynq FPGA is used to build the hardware acceleration platform of a YOLO network. The Winograd algorithm is used to improve traditional convolution. In the FPGA, the numerous multiplication operations in the YOLO network are converted into addition operations, reducing the computational complexity of the model. The data of the original model are processed at a low fixed point, reducing the resource consumption of the FPGA. To optimize memory, a buffer pipeline method is proposed, which further improves the efficiency of the designed accelerator. Experiments show that compared with the acceleration of the YOLO model based on GPUs and other FPGA platforms, the proposed method not only optimizes FPGA resource usage but also reduces power consumption to 2.7 W. Additionally, the detection accuracy loss is less than 3%.
topic	FPGA deep learning Winograd YOLO buffer pipeline
url	https://ieeexplore.ieee.org/document/9094705/
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A Power-Efficient Optimizing Framework FPGA Accelerator Based on Winograd for YOLO

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