PERFORMANCE ANALYSIS OF ADIABATIC TECHNIQUES USING FULL ADDER FOR EFFICIENT POWER DISSIPATION

• Main Authors: C. Venkatesh, A. Mohanapriya, R. Sudha Anandhi
• Format: Article
• Language: English
• Published: ICT Academy of Tamil Nadu 2018-04-01
• Series: ICTACT Journal on Microelectronics
• Subjects: adiabatic logic; low power dissipation; efficient charge recovery logic; positive feedback adiabatic logic; pass transistor logic; low power adder
• Online Access: http://ictactjournals.in/paper/IJME_Vol_4_Iss_1_Paper_2_510_514.pdf
• ISSN: 2395-1672; 2395-1680

Adiabatic circuits are low power circuits, which deals with reversible logic that it stores the power and gives it back again. Currently Several Adiabatic techniques have been adopted for efficient power dissipation. The technique used to minimize power dissipation are Efficient Charge Recovery Logic, Positive Feedback Adiabatic Logic, and Pass Transistor Logic. The Adiabatic technique is mainly used for reducing the power dissipation in VLSI circuits which performs charging and discharging process. The full adder plays an important role in many arithmetic operations such as the adder, multiplier and divider and processors. In order to limit the power dissipation, an efficient full adder is designed for the different adiabatic techniques and all the circuits have been simulated by 125nm technology using tanner EDA tool.