A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

Nanoscale CMOS technology has encountered severe reliability issues especially in on-chip memory. Conventional word-level error resilience techniques such as Error Correcting Codes (ECC) suffer from high physical overhead and inability to correct increasingly reported multiple bit flip errors. On th...

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Bibliographic Details
Main Authors: Cuiping Shao, Huiyun Li, Zheng Wang, Jiayan Fang
Format: Article
Language:English
Published: MDPI AG 2019-11-01
Series:Applied Sciences
Subjects:
principal component analysis
memory protection
error confinement
Online Access:https://www.mdpi.com/2076-3417/9/22/4733

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