Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration
This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays...
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| Format: | Article |
| Language: | English |
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MDPI AG
2018-12-01
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| Series: | Applied Sciences |
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| Online Access: | http://www.mdpi.com/2076-3417/9/1/20 |