Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

• Main Author: Yuan-Ho Chen
• Format: Article
• Language: English
• Published: MDPI AG 2018-12-01
• Series: Applied Sciences
• Subjects: field-programmable gate array (FPGA); time-to-digital converter (TDC); tapped-delay line (TDL); dual delay lines (DDL); run-time calibration; differential non-linearity (DNL)
• Online Access: http://www.mdpi.com/2076-3417/9/1/20

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.