White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology
In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of the overall chip area. On the contrast, the Xtac...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
JommPublish
2019-12-01
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| Series: | Journal of Microelectronic Manufacturing |
| Subjects: | |
| Online Access: | http://www.jommpublish.org/p/42/# |