Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique
This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple ope...
Main Authors: | Muhammad Asif, Imran Ali, Danial Khan, Muhammad Riaz Ur Rehman, Younggun Pu, Sang-Sun Yoo, Kang-Yoon Lee |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2021-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9347421/ |
Similar Items
-
A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications
by: Muhammad Asif, et al.
Published: (2020-01-01) -
Fast-Transient Low-Dropout Regulators in the IBM 0.13um BiCMOS Process
by: Duncan, Lucas
Published: (2012) -
Architectural Advancement of Digital Low-Dropout Regulators
by: Muhammad Abrar Akram, et al.
Published: (2020-01-01) -
Jaya Based ANFIS for Monitoring of Two Class Motor Imagery Task
by: Suraj, et al.
Published: (2016-01-01) -
A Wide Bandwidth High Power Supply Rejection Ratio PMOS Linear Low-Dropout Regulator With Ultra Low Quiescent Current
Published: (2020)