Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for Wasteful Overwrite
Low-power operations can be great advantageous for ReRAM devices. However, wasteful overwriting such as the SET operation to low-resistance state (LRS) device and the RESET operation to high-resistance state (HRS) device causes not only an increase in power but also the degradation of the write cycl...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2012-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2012/181395 |
| Summary: | Low-power operations can be great advantageous for ReRAM devices. However, wasteful overwriting such as the SET operation to low-resistance state (LRS) device and the RESET operation to high-resistance state (HRS) device causes not only an increase in power but also the degradation of the write cycles due to repeatedly rewriting. Thus, in this paper, we proposed a novel automatic avoidance circuit for dealing with wasteful overwriting that uses a sense amplifier and estimated the energy consumption reduction rate by conducting a circuit simulation. As a result, this circuit helped to reliably avoid the wasteful overwriting operation to reduce about 99% and 97% of wasteful energy using VSRC and CSRC, respectively. |
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| ISSN: | 0882-7516 1563-5031 |