FPGA IMPLEMENTATION OF LSB-MR BASED STEGANOGRAPHY ALGORITHMS
In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2018-04-01
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| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_Vol_4_Iss_2_Paper_2_560_565.pdf |
| Summary: | In network security Image Steganography is one of the crucial data
hiding technique. In this paper a new architecture was proposed for
with and without pipelining technique for LSB Matching Revisited
steganography algorithm and it is implemented in FPGA using Verilog
HDL. The design motto is to increasing the speed, reducing the clock
cycle by performing embedded and fetching operation parallel, reduces
the complexity in both transmitting and receiving side and also we can
send more confidential message due to the large cover image
(128×128×8) size which we have used here. In the transmitting side
data hiding is performed and receiving side extraction is performed.
Whole entire process is takes place in both hardware and software,
finally, result was analysed for both software and hardware level. From
the outcome investigation, Pipelined model will give a superior
outcome while contrasting with non-pipelining mode as far as less
inserting time contrasted with the non-pipelined mode. |
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| ISSN: | 2395-1672 2395-1680 |