Implementation of high-speed fixed-point dividers on FPGA
Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, t...
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| Format: | Article |
| Language: | English |
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Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata
2006-04-01
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| Series: | Journal of Computer Science and Technology |
| Subjects: | |
| Online Access: | https://journal.info.unlp.edu.ar/JCST/article/view/824 |