DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS

DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS

A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist fre...

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Bibliographic Details
Main Authors: Aonkar B. Takalikar, S.S. Narkhede
Format: Article
Language:English
Published: ICT Academy of Tamil Nadu 2017-07-01
Series:ICTACT Journal on Microelectronics
Subjects:
cnfet
adc
pipelined
gsps
Online Access:http://ictactjournals.in/paper/IJME_Vol_3_Iss_2_Paper_6_404_410.pdf
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spelling doaj-22a7cb295a584db19598e744401506dd2020-11-25T01:53:44ZengICT Academy of Tamil NaduICTACT Journal on Microelectronics2395-16722395-16802017-07-013240441010.21917/ijme.2017.0072DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORSAonkar B. Takalikar0S.S. Narkhede1Pune Institute of Computer Technology, India Pune Institute of Computer Technology, India A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist frequency and the ERBW is found to be 3GHz from 2 to 5GHz in which ENOB is guaranteed to be above 4.6. The average power consumed is 5.031mW for a supply voltage of 1.4V and FoM is 53.32fJ/step. http://ictactjournals.in/paper/IJME_Vol_3_Iss_2_Paper_6_404_410.pdfcnfetadcpipelinedgsps
collection DOAJ
language English
format Article
sources DOAJ
author Aonkar B. Takalikar
S.S. Narkhede
spellingShingle Aonkar B. Takalikar
S.S. Narkhede
DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS
ICTACT Journal on Microelectronics
cnfet
adc
pipelined
gsps
author_facet Aonkar B. Takalikar
S.S. Narkhede
author_sort Aonkar B. Takalikar
title DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS
title_short DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS
title_full DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS
title_fullStr DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS
title_full_unstemmed DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS
title_sort design and simulation of a 10 gsps low power sample and hold less analog to digital converter using carbon nanotube field effect transistors
publisher ICT Academy of Tamil Nadu
series ICTACT Journal on Microelectronics
issn 2395-1672
2395-1680
publishDate 2017-07-01
description A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist frequency and the ERBW is found to be 3GHz from 2 to 5GHz in which ENOB is guaranteed to be above 4.6. The average power consumed is 5.031mW for a supply voltage of 1.4V and FoM is 53.32fJ/step.
topic cnfet
adc
pipelined
gsps
url http://ictactjournals.in/paper/IJME_Vol_3_Iss_2_Paper_6_404_410.pdf
work_keys_str_mv AT aonkarbtakalikar designandsimulationofa10gspslowpowersampleandholdlessanalogtodigitalconverterusingcarbonnanotubefieldeffecttransistors
AT ssnarkhede designandsimulationofa10gspslowpowersampleandholdlessanalogtodigitalconverterusingcarbonnanotubefieldeffecttransistors
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