Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures

A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (V<sub>D</sub>) and gate (V<sub>G</sub>) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different...

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Bibliographic Details
Main Authors: Uma Sharma, Souvik Mahapatra
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
HCD
BTI
self-heating
MOSFET
DEMOS
FinFET
Online Access:https://ieeexplore.ieee.org/document/9207995/
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spelling doaj-20ecbb9c12c0433b933e9d98366b46ee2021-03-29T18:52:37ZengIEEEIEEE Journal of the Electron Devices Society2168-67342020-01-0181354136210.1109/JEDS.2020.30266299207995Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device ArchitecturesUma Sharma0https://orcid.org/0000-0002-5682-9905Souvik Mahapatra1https://orcid.org/0000-0002-4516-766XDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, IndiaA SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (V<sub>D</sub>) and gate (V<sub>G</sub>) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (&#x0394;V<sub>T</sub>), linear (&#x0394;<sub>IDLIN</sub>) and saturation (&#x0394;<sub>IDSAT</sub>) drain current and charge pumping current (&#x0394;<sub>ICP</sub>), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycle-by-cycle simulation of various Ring Oscillator (RO) circuits.https://ieeexplore.ieee.org/document/9207995/HCDBTIself-heatingMOSFETDEMOSFinFET
collection DOAJ
language English
format Article
sources DOAJ
author Uma Sharma
Souvik Mahapatra
spellingShingle Uma Sharma
Souvik Mahapatra
Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
IEEE Journal of the Electron Devices Society
HCD
BTI
self-heating
MOSFET
DEMOS
FinFET
author_facet Uma Sharma
Souvik Mahapatra
author_sort Uma Sharma
title Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
title_short Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
title_full Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
title_fullStr Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
title_full_unstemmed Modeling of HCD Kinetics Under Full V<sub>G</sub> &#x2013; V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
title_sort modeling of hcd kinetics under full v<sub>g</sub> &#x2013; v<sub>d</sub> space, different experimental conditions and across different device architectures
publisher IEEE
series IEEE Journal of the Electron Devices Society
issn 2168-6734
publishDate 2020-01-01
description A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (V<sub>D</sub>) and gate (V<sub>G</sub>) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (&#x0394;V<sub>T</sub>), linear (&#x0394;<sub>IDLIN</sub>) and saturation (&#x0394;<sub>IDSAT</sub>) drain current and charge pumping current (&#x0394;<sub>ICP</sub>), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycle-by-cycle simulation of various Ring Oscillator (RO) circuits.
topic HCD
BTI
self-heating
MOSFET
DEMOS
FinFET
url https://ieeexplore.ieee.org/document/9207995/
work_keys_str_mv AT umasharma modelingofhcdkineticsunderfullvsubgsubx2013vsubdsubspacedifferentexperimentalconditionsandacrossdifferentdevicearchitectures
AT souvikmahapatra modelingofhcdkineticsunderfullvsubgsubx2013vsubdsubspacedifferentexperimentalconditionsandacrossdifferentdevicearchitectures
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