800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm<sup>2</sup> HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V...

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Bibliographic Details
Main Authors: Peter Gillingham, David Chinn, Eric Choi, Jin-Ki Kim, Don Macdonald, Hakjune Oh, Hong-Beom Pyeon, Roland Schuetz
Format: Article
Language:English
Published: IEEE 2013-01-01
Series:IEEE Access
Subjects:
Disk drives
high speed integrated circuits
nonvolatile memory
Online Access:https://ieeexplore.ieee.org/document/6681893/
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spelling doaj-1e28e67caa6b49eb9ddc2b3dfcf90a222021-03-29T19:29:32ZengIEEEIEEE Access2169-35362013-01-01181181610.1109/ACCESS.2013.22944336681893800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring TopologyPeter Gillingham0David Chinn1Eric Choi2Jin-Ki Kim3Don Macdonald4Hakjune Oh5Hong-Beom Pyeon6Roland Schuetz7Conversant Intellectual Property Management, Inc., Ottawa, CanadaConversant Intellectual Property Management, Inc., Ottawa, CanadaConversant Intellectual Property Management, Inc., Ottawa, CanadaConversant Intellectual Property Management, Inc., Ottawa, CanadaConversant Intellectual Property Management, Inc., Ottawa, CanadaConversant Intellectual Property Management, Inc., Ottawa, CanadaConversant Intellectual Property Management, Inc., Ottawa, CanadaFounder of a software startup focused on development of equity trading algorithms and financial data analysisA 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm<sup>2</sup> HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP.https://ieeexplore.ieee.org/document/6681893/Disk driveshigh speed integrated circuitsnonvolatile memory
collection DOAJ
language English
format Article
sources DOAJ
author Peter Gillingham
David Chinn
Eric Choi
Jin-Ki Kim
Don Macdonald
Hakjune Oh
Hong-Beom Pyeon
Roland Schuetz
spellingShingle Peter Gillingham
David Chinn
Eric Choi
Jin-Ki Kim
Don Macdonald
Hakjune Oh
Hong-Beom Pyeon
Roland Schuetz
800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
IEEE Access
Disk drives
high speed integrated circuits
nonvolatile memory
author_facet Peter Gillingham
David Chinn
Eric Choi
Jin-Ki Kim
Don Macdonald
Hakjune Oh
Hong-Beom Pyeon
Roland Schuetz
author_sort Peter Gillingham
title 800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
title_short 800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
title_full 800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
title_fullStr 800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
title_full_unstemmed 800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
title_sort 800 mb/s ddr nand flash memory multi-chip package with source-synchronous interface for point-to-point ring topology
publisher IEEE
series IEEE Access
issn 2169-3536
publishDate 2013-01-01
description A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm<sup>2</sup> HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP.
topic Disk drives
high speed integrated circuits
nonvolatile memory
url https://ieeexplore.ieee.org/document/6681893/
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