A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation
Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of the filters that remove the distortion of the data. Nevertheless, a part of the available bandwidth...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/912301 |
| Summary: | Channel estimation in wireless communication systems is usually accomplished by inserting, along
with the information, a series of known symbols, whose analysis is
used to define the parameters of the filters that remove the
distortion of the data. Nevertheless, a part of the available
bandwidth has to be destined to these symbols. Until now, no
alternative solution has demonstrated to be fully satisfying for
commercial use, but one technique that looks promising is
superimposed training (ST). This work describes a hybrid
software-hardware FPGA implementation of a recent algorithm that
belongs to the ST family, known as Data-dependent Superimposed
Training (DDST), which does not need extra bandwidth for its
training sequences (TS) as it adds them arithmetically to the
data. DDST also adds a third sequence known as data-dependent
sequence, that destroys the interference caused by the data over
the TS. As DDST's computational burden is too high for the
commercial processors used in mobile systems, a System on a
Programmable Chip (SOPC) approach is used in order to solve the
problem. |
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| ISSN: | 1687-7195 1687-7209 |