The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing
Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology...
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doaj-1af0ef8f16bd4ef98eb015984544eed72021-08-20T23:00:25ZengIEEEIEEE Access2169-35362021-01-01911425511426610.1109/ACCESS.2021.31032359508983The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor ManufacturingTze Chiang Tin0https://orcid.org/0000-0002-6055-5628Saw Chin Tan1Hing Yong2https://orcid.org/0000-0002-1235-2850Jimmy Ook Hyun Kim3Eric Ken Yong Teo4Joanne Ching Yee Wong5Ching Kwang Lee6https://orcid.org/0000-0001-6696-8741Peter Than7Angela Pei San Tan8Siew Chee Phang9Faculty of Computing and Informatics, Multimedia University, Cyberjaya, MalaysiaFaculty of Computing and Informatics, Multimedia University, Cyberjaya, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaFaculty of Engineering, Multimedia University, Cyberjaya, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaX-FAB Sarawak Sdn. Bhd., Kuching, Sarawak, MalaysiaVirtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab.https://ieeexplore.ieee.org/document/9508983/Virtual metrologyoverlayclassificationregressiondata miningsmart sampling |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Tze Chiang Tin Saw Chin Tan Hing Yong Jimmy Ook Hyun Kim Eric Ken Yong Teo Joanne Ching Yee Wong Ching Kwang Lee Peter Than Angela Pei San Tan Siew Chee Phang |
spellingShingle |
Tze Chiang Tin Saw Chin Tan Hing Yong Jimmy Ook Hyun Kim Eric Ken Yong Teo Joanne Ching Yee Wong Ching Kwang Lee Peter Than Angela Pei San Tan Siew Chee Phang The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing IEEE Access Virtual metrology overlay classification regression data mining smart sampling |
author_facet |
Tze Chiang Tin Saw Chin Tan Hing Yong Jimmy Ook Hyun Kim Eric Ken Yong Teo Joanne Ching Yee Wong Ching Kwang Lee Peter Than Angela Pei San Tan Siew Chee Phang |
author_sort |
Tze Chiang Tin |
title |
The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing |
title_short |
The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing |
title_full |
The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing |
title_fullStr |
The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing |
title_full_unstemmed |
The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing |
title_sort |
implementation of a smart sampling scheme c2o utilizing virtual metrology in semiconductor manufacturing |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2021-01-01 |
description |
Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab. |
topic |
Virtual metrology overlay classification regression data mining smart sampling |
url |
https://ieeexplore.ieee.org/document/9508983/ |
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