A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems
In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2...
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MDPI AG
2017-06-01
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| Series: | Sensors |
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| Online Access: | http://www.mdpi.com/1424-8220/17/7/1497 |
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doaj-193014d87b784ee394d145d6897d41b72020-11-24T21:11:33ZengMDPI AGSensors1424-82202017-06-01177149710.3390/s17071497s17071497A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance SystemsDaehyeok Kim0Minkyu Song1Byeongseong Choe2Soo Youn Kim3Department of Semiconductor Science, Dongguk University-Seoul, Seoul 04620, KoreaDepartment of Semiconductor Science, Dongguk University-Seoul, Seoul 04620, KoreaDepartment of Information and Telecommunication Engineering, Dongguk University-Seoul, Seoul 04620, KoreaDepartment of Semiconductor Science, Dongguk University-Seoul, Seoul 04620, KoreaIn this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.http://www.mdpi.com/1424-8220/17/7/1497CMOS image sensorfixed pattern noiseintelligent surveillance system (ISS)low power consumptionmulti-mode pixel resolutiontwo-step single-slope ADC |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Daehyeok Kim Minkyu Song Byeongseong Choe Soo Youn Kim |
| spellingShingle |
Daehyeok Kim Minkyu Song Byeongseong Choe Soo Youn Kim A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems Sensors CMOS image sensor fixed pattern noise intelligent surveillance system (ISS) low power consumption multi-mode pixel resolution two-step single-slope ADC |
| author_facet |
Daehyeok Kim Minkyu Song Byeongseong Choe Soo Youn Kim |
| author_sort |
Daehyeok Kim |
| title |
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems |
| title_short |
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems |
| title_full |
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems |
| title_fullStr |
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems |
| title_full_unstemmed |
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems |
| title_sort |
multi-resolution mode cmos image sensor with a novel two-step single-slope adc for intelligent surveillance systems |
| publisher |
MDPI AG |
| series |
Sensors |
| issn |
1424-8220 |
| publishDate |
2017-06-01 |
| description |
In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates. |
| topic |
CMOS image sensor fixed pattern noise intelligent surveillance system (ISS) low power consumption multi-mode pixel resolution two-step single-slope ADC |
| url |
http://www.mdpi.com/1424-8220/17/7/1497 |
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