Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications

<p/> <p>This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow domi...

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Main Authors: Chang Chen, Ammer M Josephine, Richards Brian C, Brodersen Robert W, Kuusilinna Kimmo
Format: Article
Language:English
Published: SpringerOpen 2003-01-01
Series:EURASIP Journal on Advances in Signal Processing
Subjects:
Online Access:http://dx.doi.org/10.1155/S1110865703212154
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spelling doaj-1694aed2bd5f423cb550b3e69b7265662020-11-24T22:24:27ZengSpringerOpenEURASIP Journal on Advances in Signal Processing1687-61721687-61802003-01-0120036205943Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless ApplicationsChang ChenAmmer M JosephineRichards Brian CBrodersen Robert WKuusilinna Kimmo<p/> <p>This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.</p>http://dx.doi.org/10.1155/S1110865703212154rapid prototypingFPGAhardware emulationlow powerdesign flow
collection DOAJ
language English
format Article
sources DOAJ
author Chang Chen
Ammer M Josephine
Richards Brian C
Brodersen Robert W
Kuusilinna Kimmo
spellingShingle Chang Chen
Ammer M Josephine
Richards Brian C
Brodersen Robert W
Kuusilinna Kimmo
Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
EURASIP Journal on Advances in Signal Processing
rapid prototyping
FPGA
hardware emulation
low power
design flow
author_facet Chang Chen
Ammer M Josephine
Richards Brian C
Brodersen Robert W
Kuusilinna Kimmo
author_sort Chang Chen
title Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
title_short Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
title_full Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
title_fullStr Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
title_full_unstemmed Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
title_sort designing bee: a hardware emulation engine for signal processing in low-power wireless applications
publisher SpringerOpen
series EURASIP Journal on Advances in Signal Processing
issn 1687-6172
1687-6180
publishDate 2003-01-01
description <p/> <p>This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.</p>
topic rapid prototyping
FPGA
hardware emulation
low power
design flow
url http://dx.doi.org/10.1155/S1110865703212154
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AT richardsbrianc designingbeeahardwareemulationengineforsignalprocessinginlowpowerwirelessapplications
AT brodersenrobertw designingbeeahardwareemulationengineforsignalprocessinginlowpowerwirelessapplications
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