Low-power tunnel field effect transistors using mixed As and Sb based heterostructures
Reducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal oxide semiconductor field effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage wi...
Main Authors: | Zhu Yan, Hudait Mantu K. |
---|---|
Format: | Article |
Language: | English |
Published: |
De Gruyter
2013-12-01
|
Series: | Nanotechnology Reviews |
Subjects: | |
Online Access: | https://doi.org/10.1515/ntrev-2012-0082 |
Similar Items
-
Built-In Sheet Charge As an Alternative to Dopant Pockets in Tunnel Field-Effect Transistors`
by: Devin Verreck, et al.
Published: (2018-01-01) -
III-V Heterostructure Nanowire Tunnel FETs
by: Erik Lind, et al.
Published: (2015-01-01) -
High On-Current Ge-Channel Heterojunction Tunnel Field-Effect Transistor Using Direct Band-to-Band Tunneling
by: Garam Kim, et al.
Published: (2019-01-01) -
Strain-Engineered Biaxial Tensile Epitaxial Germanium for High-Performance Ge/InGaAs Tunnel Field-Effect Transistors
by: Michael Clavel, et al.
Published: (2015-01-01) -
F-Shaped Tunnel Field-Effect Transistor (TFET) for the Low-Power Application
by: Seunghyun Yun, et al.
Published: (2019-11-01)