Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory
For triple-level or quad-level 3D NAND flash memory, narrowing the V<sub>th</sub> distribution of each state without influencing page program performance is one of the challenges. Considering this challenge, a novel adaptive pulse programming (APP) scheme was proposed. The proposed APP s...
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doaj-152ffeab15fb421491c11d5d48b6cc4f2021-03-29T18:52:55ZengIEEEIEEE Journal of the Electron Devices Society2168-67342021-01-01910210710.1109/JEDS.2020.30410889273036Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash MemoryZhichao Du0https://orcid.org/0000-0003-4390-0343Shuang Li1Yu Wang2Xiang Fu3Fei Liu4Qi Wang5Zongliang Huo6https://orcid.org/0000-0002-9845-5649Chinese Academy of Sciences, Institute of Microelectronics, Beijing, ChinaChinese Academy of Sciences, Institute of Microelectronics, Beijing, ChinaYangtze Memory Technologies Company Ltd., Wuhan, ChinaYangtze Memory Technologies Company Ltd., Wuhan, ChinaChinese Academy of Sciences, Institute of Microelectronics, Beijing, ChinaChinese Academy of Sciences, Institute of Microelectronics, Beijing, ChinaChinese Academy of Sciences, Institute of Microelectronics, Beijing, ChinaFor triple-level or quad-level 3D NAND flash memory, narrowing the V<sub>th</sub> distribution of each state without influencing page program performance is one of the challenges. Considering this challenge, a novel adaptive pulse programming (APP) scheme was proposed. The proposed APP scheme adopted additional verify operations to separate the cells with different programming speed. It enhanced the program effect of slow cells by using increasing programming step voltage, and prevented the fast cells from over programming by using shorter programming pulse width through controlling the voltage of bitline. Compared with general incremental step pulse programming scheme, experimental results on TLC 3D NAND flash showed that, APP scheme could reduce the V<sub>th</sub> distribution width of cells by around 15% and at the same time save the program time.https://ieeexplore.ieee.org/document/9273036/3D NAND flash memoryISPP3-bit per cellVth distribution |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Zhichao Du Shuang Li Yu Wang Xiang Fu Fei Liu Qi Wang Zongliang Huo |
spellingShingle |
Zhichao Du Shuang Li Yu Wang Xiang Fu Fei Liu Qi Wang Zongliang Huo Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory IEEE Journal of the Electron Devices Society 3D NAND flash memory ISPP 3-bit per cell Vth distribution |
author_facet |
Zhichao Du Shuang Li Yu Wang Xiang Fu Fei Liu Qi Wang Zongliang Huo |
author_sort |
Zhichao Du |
title |
Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory |
title_short |
Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory |
title_full |
Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory |
title_fullStr |
Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory |
title_full_unstemmed |
Adaptive Pulse Programming Scheme for Improving the V<sub>th</sub> Distribution and Program Performance in 3D NAND Flash Memory |
title_sort |
adaptive pulse programming scheme for improving the v<sub>th</sub> distribution and program performance in 3d nand flash memory |
publisher |
IEEE |
series |
IEEE Journal of the Electron Devices Society |
issn |
2168-6734 |
publishDate |
2021-01-01 |
description |
For triple-level or quad-level 3D NAND flash memory, narrowing the V<sub>th</sub> distribution of each state without influencing page program performance is one of the challenges. Considering this challenge, a novel adaptive pulse programming (APP) scheme was proposed. The proposed APP scheme adopted additional verify operations to separate the cells with different programming speed. It enhanced the program effect of slow cells by using increasing programming step voltage, and prevented the fast cells from over programming by using shorter programming pulse width through controlling the voltage of bitline. Compared with general incremental step pulse programming scheme, experimental results on TLC 3D NAND flash showed that, APP scheme could reduce the V<sub>th</sub> distribution width of cells by around 15% and at the same time save the program time. |
topic |
3D NAND flash memory ISPP 3-bit per cell Vth distribution |
url |
https://ieeexplore.ieee.org/document/9273036/ |
work_keys_str_mv |
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