Design of a new type of general missile-borne computer based on SoC

• Main Authors: Jiang Xiaodong, Yu Jiyan
• Format: Article
• Language: zho
• Published: National Computer System Engineering Research Institute of China 2018-11-01
• Series: Dianzi Jishu Yingyong
• Subjects: missile-borne computer; common interface; parallel speedup; SoC FPGA; HLS
• Online Access: http://www.chinaaet.com/article/3000093527

In order to solve the problem such as weak calculation performance and complex sensor data interaction of the missile-borne computer in the existing guided weapons, and to improve its computing power and hardware integration, a new design of the general missile-borne computer based on the SoC FPGA is proposed. The experiment results show that the new missile-borne computer has a significant improvement of hardware integration, meanwhile, the time-consuming experiments on three platforms(ARM，DSP and SoC FPGA) have also been done. The experiment results show that compared to the traditional serial calculation method, the operation time of the new type parallel acceleration program is 4 ms, which decreases by an order of magnitude and obtains better acceleration effect. The proposed new type of general missile-borne computer has a high integration and rich interface, and the program calculation can meet the real-time and precision requirements of modern weapon guidance.