Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

• Main Authors: Yongchul Jung, Jaechan Cho, Seongjoo Lee, Yunho Jung
• Format: Article
• Language: English
• Published: MDPI AG 2019-11-01
• Series: Electronics
• Subjects: delay elements; fast fourier transform (fft); single-path delay feedback (sdf); zero-padded signal
• Online Access: https://www.mdpi.com/2079-9292/8/12/1397

This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2<inline-formula> <math display="inline"> <semantics> <msup> <mrow></mrow> <mn>2</mn> </msup> </semantics> </math> </inline-formula> and the radix-2<inline-formula> <math display="inline"> <semantics> <msup> <mrow></mrow> <mn>3</mn> </msup> </semantics> </math> </inline-formula> single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.