A Novel Defect Tolerance Scheme for Nanocrossbar Architectures with Enhanced Efficiency

• Main Authors: Devisree Sasikumar, Anand Kumar
• Format: Article
• Language: English
• Published: MDPI AG 2018-12-01
• Series: Micromachines
• Subjects: molecular switches; nanocrossbar architecture; faults; stuck-at-off; stuck-at-on; fault tolerance; maximum independent set; yield
• Online Access: http://www.mdpi.com/2072-666X/10/1/14

The semiconductor industry is now facing challenges to keep pace with Moore’s law and this leads to the requirement of new materials and newer technological devices. Molecular switch-based nanodevices are one of the promising areas because of their ultimate size and miniaturisation potential. These nanodevices are built through a self-assembled bottom-up manufacturing method in which the possibility of external intervention is negligible. This leads to a considerable yield loss due to defective device production and the traditional test-and-throw faulty device approach will not hold well. Design of fault-tolerant devices are the only possible solution. A widely studied nanodevice is nanocrossbar architectures and their fault tolerance can be designed by exploiting the programmable logic array’s fault tolerance schemes. A defect-unaware fault tolerance scheme is developed in this work based on the bipartite graph analogy of crossbar architectures. The newly-designed algorithm can eliminate more than one node in each iteration and, hence, a defect-free subcrossbar can be obtained much faster compared to the existing algorithms. A comparison with the existing defect-unaware fault-tolerant methods with this newly-developed algorithm shows a better yield in most of the cases.