AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY
Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency...
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| Online Access: | http://jestec.taylors.edu.my/Vol%2010%20issue%203%20March%202015/Volume%20(10)%20Issue%20(3)%20364-382.pdf |
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doaj-1248829086604e968f8e6af5dd0fb5db2020-11-24T22:52:48ZengTaylor's UniversityJournal of Engineering Science and Technology1823-46902015-03-01103364382AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY N. B. ROMLI0 K. N. MINHAD1M. B. I. REAZ2Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques. http://jestec.taylors.edu.my/Vol%2010%20issue%203%20March%202015/Volume%20(10)%20Issue%20(3)%20364-382.pdfCMOSDynamic powerLogic speedLow powerStatic power |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
N. B. ROMLI K. N. MINHAD M. B. I. REAZ |
| spellingShingle |
N. B. ROMLI K. N. MINHAD M. B. I. REAZ AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY Journal of Engineering Science and Technology CMOS Dynamic power Logic speed Low power Static power |
| author_facet |
N. B. ROMLI K. N. MINHAD M. B. I. REAZ |
| author_sort |
N. B. ROMLI |
| title |
AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY |
| title_short |
AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY |
| title_full |
AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY |
| title_fullStr |
AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY |
| title_full_unstemmed |
AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY |
| title_sort |
overview of power dissipation and control techniques in cmos technology |
| publisher |
Taylor's University |
| series |
Journal of Engineering Science and Technology |
| issn |
1823-4690 |
| publishDate |
2015-03-01 |
| description |
Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as
static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power
dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques. |
| topic |
CMOS Dynamic power Logic speed Low power Static power |
| url |
http://jestec.taylors.edu.my/Vol%2010%20issue%203%20March%202015/Volume%20(10)%20Issue%20(3)%20364-382.pdf |
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