A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs
Resilient circuits represent promising approaches for improving both circuit performance and tolerance for dynamic variations. However, the short path padding problem becomes severe during the implementation, resulting in significant area overhead and even frequency degradation, which might nullify...
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doaj-11ee4be7a7c54e159b345b9e191e66f32021-03-30T04:53:36ZengIEEEIEEE Access2169-35362020-01-01819025119026210.1109/ACCESS.2020.30322549231270A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit DesignsYan He0https://orcid.org/0000-0001-9695-9205Zhijian Chen1https://orcid.org/0000-0002-5844-0135Xiaoyan Xiang2https://orcid.org/0000-0002-5602-2749Taotao Zhu3https://orcid.org/0000-0002-8393-1219Institute of VLSI Design, Zhejiang University, Hangzhou, ChinaInstitute of VLSI Design, Zhejiang University, Hangzhou, ChinaDepartment of Microelectronics, Fudan University, Shanghai, ChinaInstitute of VLSI Design, Zhejiang University, Hangzhou, ChinaResilient circuits represent promising approaches for improving both circuit performance and tolerance for dynamic variations. However, the short path padding problem becomes severe during the implementation, resulting in significant area overhead and even frequency degradation, which might nullify the benefits of resilience. The present work addresses this issue by proposing a progressive resilient design methodology, including a clock period prediction method that can accurately access the minimum clock period possible in an early stage and a short path padding method, based on the greedy heuristic algorithm to reduce both the total padding delay and the runtime. The runtime for the padding stage is further minimized by introducing an accelerated padding method that decreases the number of point visits required during the greedy padding process. The proposed methodology is applied to several benchmark circuits, decreasing averagely 26.1% in the total number of padding buffers and 38.1% in the runtime, compared to a present state of the art methodology. Thus, this proposal not only avoids iterations of padding assignments by early period prediction, but also is a feasible and effective short path padding methodology for resilient circuits.https://ieeexplore.ieee.org/document/9231270/Greedy algorithmsresilienceshortest path problemultra-low voltageminimum period |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Yan He Zhijian Chen Xiaoyan Xiang Taotao Zhu |
spellingShingle |
Yan He Zhijian Chen Xiaoyan Xiang Taotao Zhu A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs IEEE Access Greedy algorithms resilience shortest path problem ultra-low voltage minimum period |
author_facet |
Yan He Zhijian Chen Xiaoyan Xiang Taotao Zhu |
author_sort |
Yan He |
title |
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs |
title_short |
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs |
title_full |
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs |
title_fullStr |
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs |
title_full_unstemmed |
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs |
title_sort |
dedicated greedy short path padding solution method for error resilient circuit designs |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2020-01-01 |
description |
Resilient circuits represent promising approaches for improving both circuit performance and tolerance for dynamic variations. However, the short path padding problem becomes severe during the implementation, resulting in significant area overhead and even frequency degradation, which might nullify the benefits of resilience. The present work addresses this issue by proposing a progressive resilient design methodology, including a clock period prediction method that can accurately access the minimum clock period possible in an early stage and a short path padding method, based on the greedy heuristic algorithm to reduce both the total padding delay and the runtime. The runtime for the padding stage is further minimized by introducing an accelerated padding method that decreases the number of point visits required during the greedy padding process. The proposed methodology is applied to several benchmark circuits, decreasing averagely 26.1% in the total number of padding buffers and 38.1% in the runtime, compared to a present state of the art methodology. Thus, this proposal not only avoids iterations of padding assignments by early period prediction, but also is a feasible and effective short path padding methodology for resilient circuits. |
topic |
Greedy algorithms resilience shortest path problem ultra-low voltage minimum period |
url |
https://ieeexplore.ieee.org/document/9231270/ |
work_keys_str_mv |
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