A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating f...

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Main Authors:	Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
Format:	Article
Language:	English
Published:	MDPI AG 2020-11-01
Series:	Electronics
Subjects:	frequency divider Current Mode Logic low power SiGe HBT design
Online Access:	https://www.mdpi.com/2079-9292/9/11/1968

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spelling	doaj-0f466fe209654b5fbcc4fbd104c15bf92020-11-25T04:11:54ZengMDPI AGElectronics2079-92922020-11-0191968196810.3390/electronics9111968A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOSFrancesco Centurelli0Pietro Monsurrò1Giuseppe Scotti2Pasquale Tommasino3Alessandro Trifiletti4Dipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni, Sapienza Università di Roma, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni, Sapienza Università di Roma, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni, Sapienza Università di Roma, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni, Sapienza Università di Roma, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni, Sapienza Università di Roma, 00184 Roma, ItalyA power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 × 65 μm<sup>2</sup> on silicon.https://www.mdpi.com/2079-9292/9/11/1968frequency dividerCurrent Mode Logiclow powerSiGe HBT design
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Francesco Centurelli Pietro Monsurrò Giuseppe Scotti Pasquale Tommasino Alessandro Trifiletti
spellingShingle	Francesco Centurelli Pietro Monsurrò Giuseppe Scotti Pasquale Tommasino Alessandro Trifiletti A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS Electronics frequency divider Current Mode Logic low power SiGe HBT design
author_facet	Francesco Centurelli Pietro Monsurrò Giuseppe Scotti Pasquale Tommasino Alessandro Trifiletti
author_sort	Francesco Centurelli
title	A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
title_short	A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
title_full	A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
title_fullStr	A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
title_full_unstemmed	A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
title_sort	power efficient frequency divider with 55 ghz self-oscillating frequency in sige bicmos
publisher	MDPI AG
series	Electronics
issn	2079-9292
publishDate	2020-11-01
description	A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 × 65 μm<sup>2</sup> on silicon.
topic	frequency divider Current Mode Logic low power SiGe HBT design
url	https://www.mdpi.com/2079-9292/9/11/1968
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A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

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