Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices

Electronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power (<inline-formula> <tex-math notation="LaTeX">$\text{P...

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Main Authors: Paul R. Berger, Albert Chin, Akira Nishiyama, Meikei Ieong
Format: Article
Language:English
Published: IEEE 2016-01-01
Series:IEEE Journal of the Electron Devices Society
Online Access:https://ieeexplore.ieee.org/document/7549245/
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spelling doaj-0abeb733030a4f94b73c33b8f80953ff2021-03-29T18:44:44ZengIEEEIEEE Journal of the Electron Devices Society2168-67342016-01-014520320410.1109/JEDS.2016.25975187549245Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic DevicesPaul R. Berger0Albert Chin1Akira Nishiyama2Meikei Ieong3Ohio State University, Columbus, OH, USANational Chiao Tung University, Hsinchu, TaiwanToshiba, JapanASTRI, Hong KongElectronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ DC}}$ </tex-math></inline-formula>) and switching AC power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ AC}}$ </tex-math></inline-formula>) consumption of future electronics must be lowered. Electronic materials play a central role for ultra-low power electronics. To lower the transistor&#x2019;s gate and source-drain leakage current, high-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> dielectric plus metal gate technologies and FinFET structures have been implemented in CMOS. The scaling of supply voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ DD}}$ </tex-math></inline-formula>) is an effective way to lower <inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ AC}}$ </tex-math></inline-formula>, where the transistor&#x2019;s current degradation can be compensated by using high mobility channel materials, such as p-channel Ge, and n-channel InGaAs; high-mobility metal-oxide semiconductors, or two-dimensional (2D) materials. The ultimate <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ DD}}$ </tex-math></inline-formula> reduction is limited by the transistor&#x2019;s turn-on slope. One proposed solution is the Tunnel FET, where carriers are injected by band-to-band-tunneling directly to the channel. Another method to reach &#x003C;60 mV/dec turn-on slope is to integrate piezoelectric or ferroelectric materials into MOSFETs. These new electronic materials can also be used for ultra-low power memory application beyond existing DRAM thereby enabling technology for processor-in-memory and brain mimicking chips.https://ieeexplore.ieee.org/document/7549245/
collection DOAJ
language English
format Article
sources DOAJ
author Paul R. Berger
Albert Chin
Akira Nishiyama
Meikei Ieong
spellingShingle Paul R. Berger
Albert Chin
Akira Nishiyama
Meikei Ieong
Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
IEEE Journal of the Electron Devices Society
author_facet Paul R. Berger
Albert Chin
Akira Nishiyama
Meikei Ieong
author_sort Paul R. Berger
title Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
title_short Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
title_full Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
title_fullStr Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
title_full_unstemmed Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices
title_sort foreword special issue on advanced technology for ultra-low power electronic devices
publisher IEEE
series IEEE Journal of the Electron Devices Society
issn 2168-6734
publishDate 2016-01-01
description Electronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ DC}}$ </tex-math></inline-formula>) and switching AC power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ AC}}$ </tex-math></inline-formula>) consumption of future electronics must be lowered. Electronic materials play a central role for ultra-low power electronics. To lower the transistor&#x2019;s gate and source-drain leakage current, high-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> dielectric plus metal gate technologies and FinFET structures have been implemented in CMOS. The scaling of supply voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ DD}}$ </tex-math></inline-formula>) is an effective way to lower <inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ AC}}$ </tex-math></inline-formula>, where the transistor&#x2019;s current degradation can be compensated by using high mobility channel materials, such as p-channel Ge, and n-channel InGaAs; high-mobility metal-oxide semiconductors, or two-dimensional (2D) materials. The ultimate <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ DD}}$ </tex-math></inline-formula> reduction is limited by the transistor&#x2019;s turn-on slope. One proposed solution is the Tunnel FET, where carriers are injected by band-to-band-tunneling directly to the channel. Another method to reach &#x003C;60 mV/dec turn-on slope is to integrate piezoelectric or ferroelectric materials into MOSFETs. These new electronic materials can also be used for ultra-low power memory application beyond existing DRAM thereby enabling technology for processor-in-memory and brain mimicking chips.
url https://ieeexplore.ieee.org/document/7549245/
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