Hierarchical Verification for the BPMN Design Model Using State Space Analysis
The BPMN design models are widely used in the software development process. Owing to the lack of BPMN standard semantics, formal verification is used to validate whether the BPMN design model is free of undesirable properties. The primary challenges of BPMN design model verification are the enormous...
Main Authors: | C. Dechsupa, W. Vatanawood, A. Thongtak |
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Format: | Article |
Language: | English |
Published: |
IEEE
2019-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/8611325/ |
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