A hybrid design approach of PVT tolerant, power efficient ring VCO

• Main Authors: Madhusudan Maiti, Suraj Kumar Saw, Abir Jyoti Mondal, Alak Majumder
• Format: Article
• Language: English
• Published: Elsevier 2020-06-01
• Series: Ain Shams Engineering Journal
• Subjects: CMOS; Current starved; VCO; Low power; Tuning range
• Online Access: http://www.sciencedirect.com/science/article/pii/S2090447919301479

This article unveils a new hybrid configuration of ring type VCO (voltage controlled oscillator) consisting of CMOS and current starved inverter to generate full voltage swing. A certain number of such inverters are cascaded alternatively to obtain the output frequency (fosc). The novelty lies in the fact that this design offers a good trade-off of power, frequency and gate count against CMOS based or current starved based design counterpart. In a 90 nm process, the highest fosc achieved for a 7th stage VCO device footprint is 1.78 GHz with a power dissipation of 44.59 µW at a supply and control voltage of 1.2 V and 1 V respectively. The simulated phase noise and output noise of the layout read to be −95.15dBc/Hz and −144.55 dB respectively measured at 1 MHz offset frequency along with the corresponding figure of merit (FOM) of −173.67dBc/Hz. In order to understand the robustness and scalability of the proposed design, the performances are observed using Monte Carlo study and as small as UMC 28 nm CMOS process.