Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios
All electronic processing components in future deep nanotechnologies will exhibit high noise level and/or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. Systems implemented with these devices would exhibit a high probability to fail, causing an...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2016-01-01
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| Series: | MATEC Web of Conferences |
| Online Access: | http://dx.doi.org/10.1051/matecconf/20164202003 |