| Summary: | For satellite communication applications, this paper presents an image rejection Ku-band low noise amplifier (LNA) in a 65-nm CMOS process for the Hartley receiver architecture. To achieve high input/output linearity performance, the inductive source degenerated cascode and the capacitive neutralized common-source (CS) amplifier topologies are used in the LNA input and output stages, respectively. To achieve wideband input return loss, the minimum noise figure and high gain performance simultaneously, the inductive source degenerated cascode amplifier is co-designed with the fourth order input impedance matching network. For the image rejection purpose, a bridged-tee band-stop filter is proposed. The measurements show the LNA achieves 14.3-to-18.3 GHz 3 dB bandwidth with 17-to-20 dB power gain, 3.5-to-4 dB noise figure, 17-to-37 dB image rejection and -5 dBm IIP3. Including all pads, the chip occupies a silicon area of 1360 × 450 μm<sup>2</sup> and consumes 72 mW DC power.
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