Reconfigurable Logic Controller—Direct FPGA Synthesis Approach

Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long respon...

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Bibliographic Details
Main Authors:	Adam Milik, Marcin Kubica, Dariusz Kania
Format:	Article
Language:	English
Published:	MDPI AG 2021-09-01
Series:	Applied Sciences
Subjects:	FPGA programmable logic controller BDD ladder diagram SFC high level synthesis
Online Access:	https://www.mdpi.com/2076-3417/11/18/8515

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spelling	doaj-03f3330e43354359b36ff78f536c8fd42021-09-25T23:40:27ZengMDPI AGApplied Sciences2076-34172021-09-01118515851510.3390/app11188515Reconfigurable Logic Controller—Direct FPGA Synthesis ApproachAdam Milik0Marcin Kubica1Dariusz Kania2Division of Digital Systems, Silesian University of Technology, 44-100 Gliwice, PolandDivision of Digital Systems, Silesian University of Technology, 44-100 Gliwice, PolandDivision of Digital Systems, Silesian University of Technology, 44-100 Gliwice, PolandProgrammable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution.https://www.mdpi.com/2076-3417/11/18/8515FPGAprogrammable logic controllerBDDladder diagramSFChigh level synthesis
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Adam Milik Marcin Kubica Dariusz Kania
spellingShingle	Adam Milik Marcin Kubica Dariusz Kania Reconfigurable Logic Controller—Direct FPGA Synthesis Approach Applied Sciences FPGA programmable logic controller BDD ladder diagram SFC high level synthesis
author_facet	Adam Milik Marcin Kubica Dariusz Kania
author_sort	Adam Milik
title	Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
title_short	Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
title_full	Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
title_fullStr	Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
title_full_unstemmed	Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
title_sort	reconfigurable logic controller—direct fpga synthesis approach
publisher	MDPI AG
series	Applied Sciences
issn	2076-3417
publishDate	2021-09-01
description	Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution.
topic	FPGA programmable logic controller BDD ladder diagram SFC high level synthesis
url	https://www.mdpi.com/2076-3417/11/18/8515
work_keys_str_mv	AT adammilik reconfigurablelogiccontrollerdirectfpgasynthesisapproach AT marcinkubica reconfigurablelogiccontrollerdirectfpgasynthesisapproach AT dariuszkania reconfigurablelogiccontrollerdirectfpgasynthesisapproach
_version_	1717368290760720384

Reconfigurable Logic Controller—Direct FPGA Synthesis Approach

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