Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new en...

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Bibliographic Details
Main Authors: Jeren Samandari-Rad, Richard Hughey
Format: Article
Language:English
Published: IEEE 2016-01-01
Series:IEEE Access
Subjects:
6T-SRAM
16-nm
leakage current
power
energy efficiency
energy-delay-product
Online Access:https://ieeexplore.ieee.org/document/7390154/
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spelling doaj-00961733201a4d5380dabc6caea8b8352021-03-29T19:38:20ZengIEEEIEEE Access2169-35362016-01-01459461310.1109/ACCESS.2016.25213857390154Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAMJeren Samandari-Rad0Richard Hughey1Electrical and Computer Engineering Departments, University of California at Santa Cruz, Santa Cruz, CA, USAComputer Engineering Department, University of California at Santa Cruz, Santa Cruz, CA, USAPower and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to minimize and predict the power/energy and power/energy variability of a 16-nm 6T-SRAM under the influence of the three major types of variations: Fabrication, Operation, and Implementation. Using exVAR-TX for architectural optimization [exhaustively computing and comparing the range of feasible architectures subject to interdie (die-to-die/D2D) and intradie (within-die/WID) process and operation variations (PVT), electromigration (EM), negative bias temperature instability (NBTI), and soft-errors, among others] on top of deploying the most recent state of the art effective mitigation techniques we show that energy and energy-delay-product (EDP) of 64KB 16-nm 6T-SRAM could be reduced by ~12.5X and ~33%, respectively, as compared to the existing conventional designs.https://ieeexplore.ieee.org/document/7390154/6T-SRAM16-nmleakage currentpowerenergy efficiencyenergy-delay-product
collection DOAJ
language English
format Article
sources DOAJ
author Jeren Samandari-Rad
Richard Hughey
spellingShingle Jeren Samandari-Rad
Richard Hughey
Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
IEEE Access
6T-SRAM
16-nm
leakage current
power
energy efficiency
energy-delay-product
author_facet Jeren Samandari-Rad
Richard Hughey
author_sort Jeren Samandari-Rad
title Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
title_short Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
title_full Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
title_fullStr Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
title_full_unstemmed Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
title_sort power/energy minimization techniques for variability-aware high-performance 16-nm 6t-sram
publisher IEEE
series IEEE Access
issn 2169-3536
publishDate 2016-01-01
description Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to minimize and predict the power/energy and power/energy variability of a 16-nm 6T-SRAM under the influence of the three major types of variations: Fabrication, Operation, and Implementation. Using exVAR-TX for architectural optimization [exhaustively computing and comparing the range of feasible architectures subject to interdie (die-to-die/D2D) and intradie (within-die/WID) process and operation variations (PVT), electromigration (EM), negative bias temperature instability (NBTI), and soft-errors, among others] on top of deploying the most recent state of the art effective mitigation techniques we show that energy and energy-delay-product (EDP) of 64KB 16-nm 6T-SRAM could be reduced by ~12.5X and ~33%, respectively, as compared to the existing conventional designs.
topic 6T-SRAM
16-nm
leakage current
power
energy efficiency
energy-delay-product
url https://ieeexplore.ieee.org/document/7390154/
work_keys_str_mv AT jerensamandarirad powerenergyminimizationtechniquesforvariabilityawarehighperformance16nm6tsram
AT richardhughey powerenergyminimizationtechniquesforvariabilityawarehighperformance16nm6tsram
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