Showing 1 - 17 results of 17 for search 'Jou, Jing-Yang', query time: 0.10s Refine Results
  1. 1
    Observability Analysis on HDL Descriptions for Effective Functional Validation and Debugging
    by Jiang, Tai-Ying, 江泰盈
    Published 2008
    Other Authors: “...Jou, Jing-Yang...”
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  2. 2
    A Weight Tuning Algorithm for Arbiters in Bus Matrix Systems
    by Chen, Kuang-Wei, 陳匡緯
    Published 2009
    Other Authors: “...Jou, Jing-Yang...”
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  3. 3
    Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
    by Hsu, Wan-Ling, 許婉玲
    Published 2009
    Other Authors: “...Jou, Jing-Yang...”
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  4. 4
    Interface Compliance Verification Using the EFSM Model
    by Shih, Che-Hua, 石哲華
    Published 2009
    Other Authors: “...Jou, Jing-Yang...”
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  5. 5
    On Design and Verification of On-chip Interconnections
    Other Authors: “...Jou, Jing-Yang...”
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  6. 6
    Delay Optimal Compressor Tree Synthesis for LUT-Based FPGAs
    by Lu, Jhih-Hong, 呂智宏
    Published 2009
    Other Authors: “...Jou, Jing-Yang...”
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  7. 7
    A Cache Hierarchy Aware Thread Mapping Methodology for Throughput Processors
    by Kuo, Hsien-Kai, 郭玹凱
    Published 2014
    Other Authors: “...Jou, Jing-Yang...”
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  8. 8
    Analytical Area Optimization for VLSI Implementations of FIR and FFT Algorithms
    by Lin, Bu-Ching, 林步青
    Published 2014
    Other Authors: “...Jou, Jing-Yang...”
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  9. 9
    Scheduling Algorithms of Co-optimizing Thread-Level- Parallelism and Cache Utilization for GPGPUs 研
    by Lu, Chin-Fu, 呂勁甫
    Published 2014
    Other Authors: “...Jou, Jing-Yang...”
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  10. 10
    The Methods on Improving Design Quality/Diagnosibility in Physical Design Stage
    by Wu, Meng-Chen, 吳孟臻
    Published 2011
    Other Authors: “...Jou, Jing-Yang...”
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  11. 11
    Precision optimization for FFT processor design using static probability-based analysis
    by Shih, Ming-En, 石銘恩
    Published 2011
    Other Authors: “...Jou, Jing-Yang...”
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  12. 12
    An Architecture-Aware Thread Mapping Methodology for Fuzzy Neural Networks on GPGPUs
    by Tseng, Hao-Yuan, 曾浩原
    Published 2012
    Other Authors: “...Jou, Jing-Yang...”
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  13. 13
    Area Minimization for FFT Processor Using Multi-Region Conditional Block Scaling
    by Chen, Po-Lin, 陳柏霖
    Published 2012
    Other Authors: “...Jou, Jing-Yang...”
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  14. 14
    A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems
    by Lai, Chih-Yen, 賴之彥
    Published 2013
    Other Authors: “...Jou, Jing-Yang...”
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  15. 15
    Design Space Exploration for Hardware-Efficient FIR Filter Design
    by Yang, Chuang-Ren, 楊創任
    Published 2012
    Other Authors: “...Jou, Jing-Yang...”
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  16. 16
    A Learning-on-Cloud Power Management Policy for Multiprocessor Smart Devices
    by Pan, Gung-Yu, 潘畊宇
    Published 2015
    Other Authors: “...Jou, Jing-Yang...”
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  17. 17
    A Parameterizable Generator for High-Performance and Low-Cost FFT Cores
    by Wang, Tu-Hsiang, 王毓翔
    Published 2009
    Other Authors: “...Jou, Jing-Yang、Huang, Juinn-Dar...”
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