Showing 1 - 20 results of 86 for search 'Jer-Min,Jou', query time: 0.09s Refine Results
  1. 1
    A Model and Design of a Distributed Hierarchical Parallel Controller
    by Po-HsienChen, 陳柏憲
    Published 2018
    Other Authors: “...Jer-Min Jou...”
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  2. 2
    Analysis and Research of Multi-level Computing Architecture
    by Shan-WenChen, 陳善文
    Published 2018
    Other Authors: “...Jer-Min Jou...”
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  3. 3
    General Accelerator Study and Design for Convolutional Neural Network
    by Yu-LinHu, 胡雨霖
    Published 2019
    Other Authors: “...Jer-Min Jou...”
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  4. 4
    A New and Efficient SVM Accelerator Design with Fixed-Width Multipliers
    by Jian-JhangChen, 陳建璋
    Published 2019
    Other Authors: “...Jer-Min Jou...”
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  5. 5
    CSR-based Deconvolution Accelerator Design
    by Xiang-YuLiao, 廖祥宇
    Published 2019
    Other Authors: “...Jer-Min Jou...”
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  6. 6
    Pipelining and Unrolling Design of a CNN Accelerator with Half Multipliers
    by Lien-ChunHu, 胡連鈞
    Published 2019
    Other Authors: “...Jer-Min Jou...”
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  7. 7
    SoC SW/HW Co-Design of A Scalable Multi-Threaded JVM
    by Yung-Chao Chen, 陳泳超
    Published 2007
    Other Authors: “...Jer-Min Jou...”
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  8. 8
    A Parallel JPEG Encoder Design on a MPSoC Platform
    by Jun-Wei Yang, 楊竣崴
    Published 2007
    Other Authors: “...Jer-Min Jou...”
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  9. 9
    Parameterized Design and Implementation of an Adaptive Multi-Symbol Arithmetic Coding Chip
    by Keng-Tang Wu, 吳肯唐
    Published 2000
    Other Authors: “...Jer-Min Jou...”
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  10. 10
    Efficient Rapid Hardware Prototyping, Analyzing and Design of A HMM-based Speech Recognition Engine
    by Cheng Jen Huang, 黃俊仁
    Published 2000
    Other Authors: “...Jer Min Jou...”
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  11. 11
    Parameterized Design and Chip Implementation of a Wavelet Based Progressive Image Coding System
    by Chin-Chi Liu, 劉晉吉
    Published 2000
    Other Authors: “...Jer-Min Jou...”
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  12. 12
    Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding
    by Hsiao-cheng Wang, 王效誠
    Published 2000
    Other Authors: “...Jer-Min Jou...”
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  13. 13
    On the Design of Data Compression and Color Correction ASICs with Some New High Level Synthesis Approaches
    by Kuang, Shiann-Rong, 鄺獻榮
    Published 1998
    Other Authors: “...Jer-Min Jou...”
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  14. 14
    Design and Implementation of An Asynchronous Adaptive Echo Canceller
    by Wu, Chau-Ching, 吳兆鈞
    Published 1998
    Other Authors: “...Jer-Min Jou...”
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  15. 15
    Performance Optimization of Sequential Circuits
    by Bu-Ren Zheng, 鄭卜仁
    Published 1994
    Other Authors: “...Jer-Min Jou...”
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  16. 16
    Study and Anylsis of A Simultaneous Multithreaded Processor
    by Chi-HungChung, 鍾旗鴻
    Published 2010
    Other Authors: “...Jer-Min Jou...”
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  17. 17
    Design and Implementation of a Cloud Computing Based Compilation Scheduling System
    by Shih-PinChen, 陳仕彬
    Published 2012
    Other Authors: “...Jer-Min Jou...”
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  18. 18
    Design of a Run-Time Dynamic Data Manager for Multi-Core Systems
    by Wen-HsienChang, 張文賢
    Published 2012
    Other Authors: “...Jer-Min Jou...”
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  19. 19
    System Level Virtual Hw/Sw Co-Design of A JPEG Encoder
    by Wei-ZheHsu, 許維哲
    Published 2012
    Other Authors: “...Jer-Min Jou...”
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  20. 20
    Design of a Dynamic Parallel Execution Architecture for Multi-Core Systems
    by ShiangHuang, 黃詳
    Published 2012
    Other Authors: “...Jer-Min Jou...”
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