Showing 1 - 20 results of 47 for search 'JIN-TAI YAN', query time: 0.13s Refine Results
  1. 1
    Post-Layout Cell Modification with Timing Consideration
    by Zhi-Wei Chen, 陳志瑋
    Published 2013
    Other Authors: “...Jin-Tai Yan...”
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  2. 2
    Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
    by Chien-Jung Huang, 黃建榮
    Published 2013
    Other Authors: “...Jin-Tai Yan...”
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  3. 3
    Timing-Driven Octilinear Steiner Tree Migration
    by HUANG, LI-CHIN, 黃麗琴
    Published 2007
    Other Authors: “...Jin-Tai Yan...”
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  4. 4
    Timing-Driven Steiner Tree Construction Based on Sharing-Buffer Insertion and Steiner-Pointt Assignment
    by Tzu-Ya Wang, 王姿雅
    Published 2005
    Other Authors: “...Jin-Tai Yan...”
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  5. 5
    Obstacle-Aware Multiple-Source Steiner Tree Construction for Electromigration and IR-Drop Avoidance
    by HSIANG-LIN KE, 柯祥霖
    Published 2010
    Other Authors: “...JIN-TAI YAN...”
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  6. 6
    OPE-aware Redundant Wire Insertion for Zero-Skew Clock Tree Construction
    by Yu-Cheng Chang, 張育誠
    Published 2011
    Other Authors: “...Jin-Tai Yan...”
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  7. 7
    Validating and Overcoming the Effect of Corruption Error on FlexRay Communication Systems
    by Shie-Lung Li, 李協龍
    Published 2011
    Other Authors: “...Jin-Tai Yan...”
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  8. 8
    Routability-Driven RDL Routing With Pin-Reassignment
    by Ke-Chyuan Chen, 陳科銓
    Published 2011
    Other Authors: “...Jin-Tai Yan...”
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  9. 9
    Simultaneous Escape Routing Between Two Chips Based on Determination of Routability-Driven Net Order
    by Tung-Yen Sung, 宋東彥
    Published 2011
    Other Authors: “...Jin-Tai Yan...”
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  10. 10
    Correctness Computation of a Probabilistic Combinational Circuit with Application to Arithmetic Circuits
    by Chia-Han Kao, 高佳涵
    Published 2012
    Other Authors: “...Jin-Tai Yan...”
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  11. 11
    High-Performance Zero-Skew Clock Tree Construction on SoC Design
    by Chiao-Ling Lung, 龍巧玲
    Published 2002
    Other Authors: “...Jin-Tai Yan...”
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  12. 12
    Area-Driven Buffer Block Planning with Optimal Wire-Sizing Assignment
    by Chao-Hung Lu, 呂昭宏
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  13. 13
    Congestion-Driven Global Routing Based on Timing-Constrained Routing Flexibilities
    by Shun-Hua Lin, 林順華
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  14. 14
    Hierarchical Timing-Constrained Full-Chip Routing System
    by Yen-Hsiang Chen, 陳彥翔
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  15. 15
    Dynamic Tree Reconstruction for Timing-Constrained Congestion-Driven Global Routing
    by Chia Fang Lee, 李佳芳
    Published 2004
    Other Authors: “...Jin Tai Yan...”
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  16. 16
    An Integrated Approach for Floorplan and Routing Strategies with Crosstalk Minimization
    by Feng-Ming Chen, 陳逢銘
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  17. 17
    Temperature-Constrained Thermal-Driven Floorplan on DBL Representation
    by Jen-jy Chen, 陳正智
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  18. 18
    HDBL(Hierarchical Double-Bound List):A Multilevel Floorplan Representation for Large-Scale Modules
    by Chen Chieh-Huang, 陳杰煌
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  19. 19
    Congestion-Driven Floorplan on DBL Representation
    by Chien-Chen Su, 蘇乾禎
    Published 2004
    Other Authors: “...Jin-Tai Yan...”
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  20. 20
    具有避開障礙物之三度空間時序導向史丹爾樹之建構
    by Dun-Hao Hu, 胡惇皓
    Published 2008
    Other Authors: “...Jin-Tai Yan...”
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