Showing 1 - 20 results of 45 for search 'Huang Juinn-Dar', query time: 0.09s Refine Results
  1. 1
    Logic Synthesis and Partitioning for FPGAs
    by Huang, Juinn-Dar, 黃俊達
    Published 1998
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  2. 2
    A Dual-Convolver Based CNN Accelerator Achieving High Computing Resource Utilization
    by Lu, Yi, 盧毅
    Published 2019
    Other Authors: “...Huang, Juinn-Dar...”
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  3. 3
    Test Pattern Generation with High Fault Coverage for Irregular Digital Microfluidic Biochips
    by Yu, Chieh-Ming, 游傑閔
    Published 2019
    Other Authors: “...Huang, Juinn-Dar...”
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  4. 4
    Sample Preparation for Reactant Minimization on MEDA-Based DMFBs using Partial Fraction Decomposition
    by Wen, Ren-Hong, 温仁弘
    Published 2019
    Other Authors: “...Huang, Juinn-Dar...”
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  5. 5
    High-Level Synthesis on Various Distributed Register Architectures
    by Chen, Chia-I, 陳嘉怡
    Published 2013
    Other Authors: “...Huang, Juinn-Dar...”
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  6. 6
    Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on DMFBs
    by Yeh, Chih-Shen, 葉志燊
    Published 2018
    Other Authors: “...Huang, Juinn-Dar...”
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  7. 7
    Time-Constrained Sample Preparation Algorithm for Reactant Minimization on DMFBs
    by Li, Yu-Ying, 李育瑛
    Published 2018
    Other Authors: “...Huang, Juinn-Dar...”
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  8. 8
    Probability-Based Sample Preparation for Unbalanced Splitting Correction on DMFBs
    by Chen, Yi-Ling, 陳奕伶
    Published 2018
    Other Authors: “...Huang, Juinn-Dar...”
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  9. 9
    Many-Reactant and Multi-Target Sample Preparation on Flow-Based Microfluidic Biochips
    by Wu, Shi-Yu, 吳錫御
    Published 2017
    Other Authors: “...Huang, Juinn-Dar...”
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  10. 10
    Architecture Exploration and Delay Minimization Synthesis for SET-Based Field Programmable Gate Arrays
    by Ho, Kung-Han, 何公瀚
    Published 2017
    Other Authors: “...Huang, Juinn-Dar...”
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  11. 11
    Thorough Defect Diagnosis for Reconfigurable Single-Electron Transistor Arrays
    by Hu, Yi-Hsiang, 胡翊翔
    Published 2018
    Other Authors: “...Huang, Juinn-Dar...”
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  12. 12
    Low Power Multiplexer Tree Design Using Dynamic Input Selection Control
    by Li Nan-Shing, 李南興
    Published 2007
    Other Authors: “...Huang Juinn-Dar...”
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  13. 13
    Efficient MP3 Decoder System using a 32-bit Low-Power Embedded Processor Core
    by Hsin, Wei-Kuo, 辛威虢
    Published 2009
    Other Authors: “...Huang, Juinn-Dar...”
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  14. 14
    HIGH-PERFORMANCE NAND FLASH CONTROLLER
    by Kao, Yu-Hsiang, 高于翔
    Published 2009
    Other Authors: “...Huang, Juinn-Dar...”
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  15. 15
    Script-Controlled Constrained-Random Pattern Generator for Processor Verification
    by Hsu, Han-Wei, 許瀚蔚
    Published 2009
    Other Authors: “...Huang, Juinn-Dar...”
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  16. 16
    Communication Synthesis on Distributed Register-File Microarchitecture
    by Lin, Yen-Ting, 林彥廷
    Published 2009
    Other Authors: “...Huang, Juinn-Dar...”
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  17. 17
    Throughput Optimization for Latency Insensitive System with Minimal Buffer Size
    by Ho, Ya-Chien, 何亞謙
    Published 2009
    Other Authors: “...Huang, Juinn-Dar...”
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  18. 18
    A Parallel Layer-Aware Partitioning Algorithm for TSV Minimization in 3D ICs
    by Chen, Yi-Ting, 陳怡廷
    Published 2013
    Other Authors: “...Huang, Juinn-Dar...”
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  19. 19
    Sample Preparation for Many-Reactant Bioassay on DMFBs using Common Dilution Operation Sharing
    by Chang, Hao-Han, 張顥瀚
    Published 2014
    Other Authors: “...Huang, Juinn-Dar...”
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  20. 20
    High-Speed and Area-Minimized FIR Filter Design using Memory-Based Multiplication on FPGAs
    by Hsu, Jin-Wei, 許晉維
    Published 2012
    Other Authors: “...Huang, Juinn-Dar...”
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