10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

by Paolo Visconti, Stefano Capoccia, Eugenio Venere, Ramiro Velázquez, Roberto de Fazio
Published 2020-10-01