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Chung, Shao-Shiun
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Chung, Shao-Shiun
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Chung, Shao-Shiun
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1
Design of the Complementary Face-Tunneling FET for Ultra-low Power Applications
by
Zhao, Yu-Bin
,
趙堉斌
Published 2015
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Chung
,
Shao
-
Shiun
...
”
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2
Experimental Determination of the Ballistic Transport Characteristics of Nanoscale Trigate MOSFETs
by
Lin, Tsung-Ching
,
林宗慶
Published 2013
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...
Chung
,
Shao
-
Shiun
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3
The Design and Optimization of a Low Power Bi-layer Resistance RAM
by
Yang, Shang-Po
,
楊勝博
Published 2015
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...
Chung
,
Shao
-
Shiun
...
”
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4
New Understandings on the Correlation Between Work-function Fluctuation and Vth Variation in HKMG CMOS Devices
by
Wang, Yuan-Ding
,
王元鼎
Published 2015
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Chung
,
Shao
-
Shiun
...
”
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5
The Impact of the Shallow Trench Isolation on the Reliability of Trigate MOSFET
by
Wu, Chia-Wei
,
吳嘉偉
Published 2015
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Chung
,
Shao
-
Shiun
...
”
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6
A One-Time-Programmable Array Based on a New Dielectric Fuse Breakdown Mechanism
by
Huang, Zhi-Hong
,
黃智宏
Published 2015
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Chung
,
Shao
-
Shiun
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