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Chi Nan Chuang
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Chi Nan Chuang
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Chi Nan Chuang
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1
The design of a frequency synthesizers and a clock & data recovery circuits in 0.35um CMOS process
by
chi
-
nan
chuang
,
莊基男
Published 2003
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2
Research On Abnormal Transaction Detection Of Banking Account
by
Chi
-
Nan
Chuang
,
莊啟男
Published 2007
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Others
3
Design of High Speed Delay-Locked Loops
by
Chi
-
Nan
Chuang
,
莊基男
Published 2008
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Others
4
Human Machine Interface Design of Internet of Things
by
Tzung-Rung Wu
,
吳宗融
Published 2018
Other Authors:
“
...
Chi
-
Nan
Chuang
...
”
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5
Semiconductor Technology and Life Research
by
Chien AN Liao
,
廖建安
Published 2013
Other Authors:
“
...
Chi
Nan
Chuang
...
”
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6
Design and Implementation of a 5GHz Frequency Synthesizer for Wireless Application
by
YE,SHANG-LUN
,
葉上綸
Published 2013
Other Authors:
“
...
Chi
-
Nan
Chuang
...
”
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7
Design and Implementation of Wide-Range Multi-phase Delay-Locked Loop
by
HONG-JIE GUO
,
郭鴻傑
Published 2013
Other Authors:
“
...
Chi
-
Nan
Chuang
...
”
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8
Design and Implementation of DLL-Based Pulse-Width Controlled Loop
by
Hao-Fan Chen
,
陳皓汎
Published 2012
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...
Chi
-
Nan
Chuang
...
”
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9
Design And Implementation Of High-Bandwidth Phase-Locked Loop
by
Jian-Ji Zhang
,
張見吉
Published 2012
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...
Chi
-
Nan
Chuang
...
”
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10
Design of Phase-Locked Loop With Reference Clock Injection to Improve Loop-Bandwidth
by
Kao, Chen-hsiang
,
高振翔
Published 2016
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Chi
Nan
Chuang
...
”
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11
Design of Injection-Locked Low Noise PLL
by
LIU,SHAO-CHUN
,
劉劭軍
Published 2016
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Chi
Nan
Chuang
...
”
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12
Design and application of PLL for wide range and low noise
by
YUE TENG LIOU
,
劉岳縢
Published 2013
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Chi
Nan
Chuang
...
”
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13
Design and Implementation Driving Signal of High-Resolution Panel
by
Yang Chun Huang
,
黃揚淳
Published 2014
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...
Chi
Nan
Chuang
...
”
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14
A High Speed DLL-Based Clock Generator With High Multiplication Ratio
by
Sheng Huai Cheng
,
鄭聖懷
Published 2015
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...
Chi
Nan
Chuang
...
”
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